mirror of
https://github.com/official-stockfish/Stockfish.git
synced 2026-07-22 12:47:08 +00:00
[RfC] RISC-V port and universal binary
Performance on Spacemit K3, thanks @edolnx for testing master: Total time (ms) : 65200 Nodes searched : 3493826 Nodes/second : 53586 riscv-scalable-port: Total time (ms) : 15834 Nodes searched : 3493826 Nodes/second : 220653 Also thanks to @camel-cdr for guidance on RVV programming, and https://cloud-v.co for supplying an RVV instance to test with passed STC: LLR: 2.81 (-2.94,2.94) <0.00,2.00> Total: 1152 W: 527 L: 108 D: 517 Ptnml(0-2): 0, 17, 167, 348, 44 https://tests.stockfishchess.org/tests/view/6a39895b3036e45021aeb368 ## Summary We've had a `riscv64` target for a while, but haven't really optimized for it, in particular the vector extension (RVV). RVV, like SVE, is based on a scalable vector system where the vector length ranges from 128 to 65536. In practice implementations are between 128 and 2048, and 256 bits is quite common (e.g. the Spacemit K3 system above). Unfortunately this doesn't fit well into the rest of our code which assumes a fixed vector length, so what I've done is bypass the `VECTOR` ifdef (which now basically means "FIXED_LENGTH_VECTOR") and just have RVV-specific paths. The ability to explicitly control `vl` makes the code quite readable, in my opinion. We use LMUL>1 in most places to take advantage of multi-vector instructions. Generally the LMULs were chosen to best support a 256-bit vlen, which is very common, but by virtue of how the vlen control works, the code works with any vlen. In a couple places, i.e., `get_changed_pieces` and `AffineTransformSparseInput::propagate`, we have separate implementations depending on the vlen, because the optimal LMUL varies a lot between implementations. One little wrinkle is that `load_as` is compiled to a sequence of byte loads, because although unaligned loads are legal in RVA23, the spec says that they *may* be extremely slow (even though they usually aren't, in actual hw), so compilers are conservative. Thus I aligned the relevant buffers and made the semantics of `load_as` that the operand is aligned, by adding a runtime assertion. ### Universal binary Adding a universal binary is pretty easy and we can just cross-compile. There are two targets: baseline rv64gc and riscv64-rva23, which is actually a smaller subset of RVA23 that also works on some older processors that don't support the full thing. We use clang because GCC, until recently, has a nasty bug with LTO and RVV. Like the universal ARM and x86 builds, we check all the builds in CI. In this case we run bench with multiple vlens, 128 through 1024. In the meantime I deleted the existing broken and unused riscv64 tests. ### Follow-ups - Optimizations - zvdot4a8i path closes https://github.com/official-stockfish/Stockfish/pull/6920 No functional change
This commit is contained in:
anematode
committed by
Joost VandeVondele
Joost VandeVondele
parent
99489f57dd
commit
d5bbc6b67d
+31
-15
@@ -83,7 +83,7 @@ SRCS = attacks.cpp benchmark.cpp bitboard.cpp evaluate.cpp main.cpp \
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nnue/features/half_ka_v2_hm.cpp nnue/features/full_threats.cpp \
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engine.cpp score.cpp memory.cpp
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OTHER_SRCS = universal/entry_x86.cpp universal/entry_arm64.cpp universal/nnue_embed.cpp
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OTHER_SRCS = universal/entry_x86.cpp universal/entry_arm64.cpp universal/entry_riscv64.cpp universal/nnue_embed.cpp
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HEADERS = attacks.h benchmark.h bitboard.h evaluate.h misc.h movegen.h movepick.h history.h \
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nnue/nnue_misc.h nnue/features/half_ka_v2_hm.h nnue/features/full_threats.h \
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@@ -160,13 +160,13 @@ ifeq ($(ARCH), $(filter $(ARCH), \
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x86-64-bmi2 x86-64-avx2 x86-64-sse41-popcnt x86-64-modern x86-64-ssse3 x86-64-sse3-popcnt \
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x86-64 x86-32-sse41-popcnt x86-32-sse2 x86-32 ppc-64 ppc-64-altivec ppc-64-vsx ppc-32 e2k \
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armv7 armv7-neon armv8 armv8-dotprod arm64-universal apple-silicon general-64 general-32 riscv64 \
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loongarch64 loongarch64-lsx loongarch64-lasx wasm32 wasm32-relaxed-simd))
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riscv64-rva23 riscv64-universal loongarch64 loongarch64-lsx loongarch64-lasx wasm32 wasm32-relaxed-simd))
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SUPPORTED_ARCH=true
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else
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SUPPORTED_ARCH=false
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endif
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ifneq (,$(filter $(ARCH),x86-64-universal arm64-universal))
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ifneq (,$(filter $(ARCH),x86-64-universal arm64-universal riscv64-universal))
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UNIVERSAL_BUILD=true
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else
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UNIVERSAL_BUILD=false
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@@ -195,6 +195,7 @@ vsx = no
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neon = no
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dotprod = no
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arm_version = 0
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rva23 = no
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lsx = no
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lasx = no
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relaxedsimd = no
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@@ -459,10 +460,16 @@ ifeq ($(findstring e2k,$(ARCH)),e2k)
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popcnt = yes
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endif
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ifeq ($(ARCH),riscv64)
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ifeq ($(findstring riscv64,$(ARCH)),riscv64)
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arch = riscv64
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endif
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ifeq ($(ARCH),riscv64-rva23)
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rva23 = yes
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popcnt = yes
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prefetch = yes
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endif
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ifeq ($(findstring loongarch64,$(ARCH)),loongarch64)
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arch = loongarch64
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prefetch = yes
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@@ -509,9 +516,6 @@ ifeq ($(COMP),gcc)
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CXXFLAGS += -m$(bits)
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LDFLAGS += -m$(bits)
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endif
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ifeq ($(ARCH),riscv64)
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CXXFLAGS += -latomic
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endif
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else ifeq ($(arch),loongarch64)
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CXXFLAGS += -latomic
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else ifneq ($(arch),wasm32)
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@@ -583,9 +587,6 @@ ifeq ($(COMP),clang)
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CXXFLAGS += -m$(bits)
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LDFLAGS += -m$(bits)
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endif
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ifeq ($(ARCH),riscv64)
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CXXFLAGS += -latomic
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endif
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else ifeq ($(arch),loongarch64)
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CXXFLAGS += -latomic
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else
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@@ -771,7 +772,7 @@ else
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endif
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ifeq ($(popcnt),yes)
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ifeq ($(arch),$(filter $(arch),ppc64 ppc64-altivec ppc64-vsx armv7 armv8 arm64))
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ifeq ($(arch),$(filter $(arch),ppc64 ppc64-altivec ppc64-vsx armv7 armv8 arm64 riscv64))
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CXXFLAGS += -DUSE_POPCNT
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else
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CXXFLAGS += -msse3 -mpopcnt -DUSE_POPCNT
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@@ -870,6 +871,10 @@ ifeq ($(dotprod),yes)
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CXXFLAGS += -march=armv8.2-a+dotprod -DUSE_NEON_DOTPROD
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endif
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ifeq ($(rva23),yes)
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CXXFLAGS += -march=rv64gcv1p0_zba_zbb_zbs_zicbop_zicond -DUSE_RVV
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endif
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ifeq ($(lasx),yes)
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CXXFLAGS += -DUSE_LASX
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ifeq ($(comp),$(filter $(comp),gcc clang mingw icx))
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@@ -1047,6 +1052,8 @@ help:
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echo "general-64 > unspecified 64-bit" && \
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echo "general-32 > unspecified 32-bit" && \
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echo "riscv64 > RISC-V 64-bit" && \
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echo "riscv64-rva23 > RISC-V 64-bit RVA23 profile" && \
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echo "riscv64-universal > RISC-V 64-bit with automatic runtime selection of the best architecture" && \
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echo "loongarch64 > LoongArch 64-bit" && \
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echo "loongarch64-lsx > LoongArch 64-bit with SIMD eXtension" && \
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echo "loongarch64-lasx > LoongArch 64-bit with Advanced SIMD eXtension" && \
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@@ -1383,6 +1390,11 @@ ifeq ($(arch),x86_64)
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UNIVERSAL_ENTRY_OBJ := $(TEMP_DIR)/entry_x86.o
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UNIVERSAL_ENTRY_SRC := $(UNIVERSAL_SRC_DIR)/entry_x86.cpp
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BASELINE_ARCH := x86-64
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else ifeq ($(arch),riscv64)
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UNIVERSAL_ARCHES := riscv64 riscv64-rva23
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UNIVERSAL_ENTRY_OBJ := $(TEMP_DIR)/entry_riscv64.o
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UNIVERSAL_ENTRY_SRC := $(UNIVERSAL_SRC_DIR)/entry_riscv64.cpp
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BASELINE_ARCH := riscv64
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else
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UNIVERSAL_ARCHES := armv8 armv8-dotprod
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UNIVERSAL_ENTRY_OBJ := $(TEMP_DIR)/entry_arm64.o
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@@ -1452,7 +1464,11 @@ arch-cxxflags = $(EMBED_DIR) -DStockfish=$(call arch-namespace,$(1)) -DUNIVERS
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$(call arch-defmain,$(1)) -Wno-c++26-extensions -Wno-c23-extensions
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UOBJ_TGT ?= universal-object-pgo
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OBJCOPY ?= objcopy
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ifeq ($(COMP),clang)
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OBJCOPY ?= llvm-objcopy
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else
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OBJCOPY ?= objcopy
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endif
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.PHONY: build profile-build universal-clean
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build: UOBJ_TGT := universal-object-nopgo
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@@ -1469,10 +1485,10 @@ $(NET_SENTINEL): | $(TEMP_DIR)
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@touch $@
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$(NNUE_EMBED_OBJ): $(UNIVERSAL_SRC_DIR)/nnue_embed.cpp $(NET_SENTINEL) | $(TEMP_DIR)
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$(CXX) -O2 -std=c++20 -Wno-c++26-extensions $(SLICE_DEF) $(mac_target_flags) $(EMBED_DIR) -c $< -o $@
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$(CXX) -O2 -std=c++20 -Wno-c++26-extensions $(SLICE_DEF) $(mac_target_flags) $(EXTRACXXFLAGS) $(EMBED_DIR) -c $< -o $@
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$(UNIVERSAL_ENTRY_OBJ): $(UNIVERSAL_ENTRY_SRC) | $(TEMP_DIR)
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$(CXX) -O2 -std=c++20 $(mac_target_flags) -c $< -o $@
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$(CXX) -O2 -std=c++20 $(mac_target_flags) $(EXTRACXXFLAGS) -c $< -o $@
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# Symlink tracked top-level items from src/ into temp_builds/<arch>/.
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$(TEMP_DIR)/%/.setup: | $(TEMP_DIR)
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@@ -1510,7 +1526,7 @@ endif
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endif
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$(UNIVERSAL_EXE): $(UNIVERSAL_ENTRY_OBJ) $(NNUE_EMBED_OBJ) $(ARCH_OBJS)
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$(CXX) -o $@ $(UNIVERSAL_ENTRY_OBJ) $(NNUE_EMBED_OBJ) $(ARCH_OBJS) $(UNIVERSAL_FINAL_FLAGS)
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$(CXX) -o $@ $(UNIVERSAL_ENTRY_OBJ) $(NNUE_EMBED_OBJ) $(ARCH_OBJS) $(UNIVERSAL_FINAL_FLAGS) $(EXTRALDFLAGS)
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@echo "Universal binary built: $@"
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endif # UNIVERSAL_BUILD
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@@ -20,6 +20,7 @@
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#define MEMORY_H_INCLUDED
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#include <algorithm>
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#include <cassert>
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#include <cstdint>
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#include <memory>
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#include <new>
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@@ -326,6 +327,14 @@ T load_as(const ByteT* buffer) {
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static_assert(std::is_trivially_copyable<T>::value, "Type must be trivially copyable");
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static_assert(sizeof(ByteT) == 1);
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if (reinterpret_cast<uintptr_t>(buffer) % alignof(T) != 0)
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{
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assert(false);
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#ifdef __GNUC__
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__builtin_unreachable();
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#endif
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}
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T value;
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std::memcpy(&value, buffer, sizeof(T));
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@@ -105,6 +105,26 @@ affine_transform_non_ssse3(i32* output, const i8* weights, const i32* biases, co
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#endif
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}
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#elif defined(USE_RVV)
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for (IndexType i = 0; i < OutputDimensions; ++i)
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{
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const i8* row = &weights[i * PaddedInputDimensions];
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vint32m1_t vsum = __riscv_vmv_v_x_i32m1(0, __riscv_vsetvlmax_e32m1());
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for (usize j = 0; j < InputDimensions;)
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{
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usize vl = __riscv_vsetvl_e8m4(InputDimensions - j);
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vint8m4_t w = __riscv_vle8_v_i8m4(&row[j], vl);
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vuint8m4_t x = __riscv_vle8_v_u8m4(&input[j], vl);
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vint16m8_t prod = __riscv_vwmulsu_vv_i16m8(w, x, vl);
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vsum = __riscv_vwredsum_vs_i16m8_i32m1(prod, vsum, vl);
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j += vl;
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}
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output[i] = biases[i] + __riscv_vmv_x_s_i32m1_i32(vsum);
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}
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#else
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std::memcpy(output, biases, sizeof(i32) * OutputDimensions);
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@@ -59,7 +59,8 @@ class AffineTransformSparseInput {
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static constexpr IndexType PaddedOutputDimensions =
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ceil_to_multiple<IndexType>(OutputDimensions, MaxSimdWidth);
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#if (defined(USE_SSSE3) || defined(USE_LSX) || defined(USE_LASX) || (USE_NEON >= 8))
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#if (defined(USE_SSSE3) || defined(USE_LSX) || defined(USE_LASX) || (USE_NEON >= 8) \
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|| defined(USE_RVV))
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static constexpr IndexType ChunkSize = 4;
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#else
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static constexpr IndexType ChunkSize = 1;
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@@ -82,7 +83,8 @@ class AffineTransformSparseInput {
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}
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static constexpr IndexType get_weight_index(IndexType i) {
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#if (defined(USE_SSSE3) || defined(USE_LSX) || defined(USE_LASX) || (USE_NEON >= 8))
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#if (defined(USE_SSSE3) || defined(USE_LSX) || defined(USE_LASX) || (USE_NEON >= 8) \
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|| defined(USE_RVV))
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return get_weight_index_scrambled(i);
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#else
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return i;
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@@ -275,6 +277,51 @@ class AffineTransformSparseInput {
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#ifdef vec_add_32
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#undef vec_add_32
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#endif
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#elif defined(USE_RVV)
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static_assert(InputDimensions % 256 == 0);
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const i8* weights_cp = weights;
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#define RVV_SPARSE_PROPAGATE(LMUL) \
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do \
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{ \
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const usize blk = __riscv_vsetvlmax_e32m##LMUL(); \
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for (IndexType ob = 0; ob < OutputDimensions; ob += blk) \
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{ \
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const usize vl = __riscv_vsetvl_e32m##LMUL(OutputDimensions - ob); \
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vint32m##LMUL##_t acc = __riscv_vle32_v_i32m##LMUL(biases + ob, vl); \
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for (IndexType k = 0; k < InputDimensions / 256; ++k) \
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{ \
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u64 bits = load_as<u64>(nnzInfo.bitset + k * 8); \
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isize base = k * 64; \
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auto* base_addr = input + base * sizeof(i32); \
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auto* weights_base = &weights_cp[base * OutputDimensions * ChunkSize]; \
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while (bits) \
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{ \
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isize i = pop_lsb(bits); \
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vuint8m##LMUL##_t a = __riscv_vreinterpret_v_u32m##LMUL##_u8m##LMUL( \
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__riscv_vmv_v_x_u32m##LMUL(load_as<u32>(base_addr + i * sizeof(i32)), \
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vl)); \
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vint8m##LMUL##_t b = __riscv_vle8_v_i8m##LMUL( \
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&weights_base[i * OutputDimensions * ChunkSize + ob * ChunkSize], \
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vl * ChunkSize); \
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acc = \
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__riscv_vadd_vv_i32m##LMUL(acc, SIMD::rvv_dpbusd_m##LMUL(a, b, vl), vl); \
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} \
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} \
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__riscv_vse32_v_i32m##LMUL(output + ob, acc, vl); \
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} \
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} while (0)
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// Select LMUL
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if (__riscv_vsetvlmax_e32m1() >= OutputDimensions)
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RVV_SPARSE_PROPAGATE(1);
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else if (__riscv_vsetvlmax_e32m2() >= OutputDimensions)
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RVV_SPARSE_PROPAGATE(2);
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else
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RVV_SPARSE_PROPAGATE(4);
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#undef RVV_SPARSE_PROPAGATE
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#else
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// Use dense implementation for the other architectures.
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affine_transform_non_ssse3<InputDimensions, PaddedInputDimensions, OutputDimensions>(
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@@ -147,6 +147,24 @@ class ClippedReLU {
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}
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constexpr IndexType Start = NumChunks * 16;
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#elif defined(USE_RVV)
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for (usize j = 0; j < InputDimensions;)
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{
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usize vl = __riscv_vsetvl_e32m4(InputDimensions - j);
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vint32m4_t in = __riscv_vle32_v_i32m4(&input[j], vl);
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in = __riscv_vmax_vx_i32m4(in, 0, vl);
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vint16m2_t words =
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__riscv_vnclip_wx_i16m2(in, WeightScaleBitsLocal, __RISCV_VXRM_RDN, vl);
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vint8m1_t narrowed = __riscv_vnclip_wx_i8m1(words, 0, __RISCV_VXRM_RDN, vl);
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__riscv_vse8_v_u8m1(&output[j], __riscv_vreinterpret_v_i8m1_u8m1(narrowed), vl);
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j += vl;
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}
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constexpr IndexType Start = InputDimensions;
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#else
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constexpr IndexType Start = 0;
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#endif
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@@ -143,6 +143,22 @@ class SqrClippedReLU {
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}
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constexpr IndexType Start = NumChunks * 16;
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#elif defined(USE_RVV)
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for (usize j = 0; j < InputDimensions;)
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{
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usize vl = __riscv_vsetvl_e32m4(InputDimensions - j);
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vint32m4_t in = __riscv_vle32_v_i32m4(&input[j], vl);
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vint16m2_t words = __riscv_vnclip_wx_i16m2(in, 0, __RISCV_VXRM_RDN, vl);
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vint16m2_t sqr = __riscv_vmulh_vv_i16m2(words, words, vl);
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vint8m1_t narrowed = __riscv_vnclip_wx_i8m1(sqr, SimdShiftAmount, __RISCV_VXRM_RDN, vl);
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__riscv_vse8_v_u8m1(&output[j], __riscv_vreinterpret_v_i8m1_u8m1(narrowed), vl);
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j += vl;
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}
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constexpr IndexType Start = InputDimensions;
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#else
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constexpr IndexType Start = 0;
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#endif
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@@ -288,6 +288,64 @@ void apply_combined(Color perspective,
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vec_store_psqt(&toTilePsqt[k], psqt[k]);
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}
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#elif defined(USE_RVV)
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usize tileOffset = 0;
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const auto* psqWeights = &featureTransformer.weights[0];
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const auto* threatWeights = &featureTransformer.threatWeights[0];
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const auto* psqtWeights = &featureTransformer.psqtWeights[0];
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const auto* threatPsqtWeights = &featureTransformer.threatPsqtWeights[0];
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while (tileOffset < Dimensions)
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{
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usize vl = __riscv_vsetvl_e16m8(Dimensions - tileOffset);
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vint16m8_t accum = __riscv_vle16_v_i16m8(&fromAcc[tileOffset], vl);
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for (int i : psqRemoved)
|
||||
accum = __riscv_vsub_vv_i16m8(
|
||||
accum, __riscv_vle16_v_i16m8(&psqWeights[i * Dimensions + tileOffset], vl), vl);
|
||||
for (int i : psqAdded)
|
||||
accum = __riscv_vadd_vv_i16m8(
|
||||
accum, __riscv_vle16_v_i16m8(&psqWeights[i * Dimensions + tileOffset], vl), vl);
|
||||
for (int i : thrRemoved)
|
||||
accum = __riscv_vwsub_wv_i16m8(
|
||||
accum, __riscv_vle8_v_i8m4(&threatWeights[i * Dimensions + tileOffset], vl), vl);
|
||||
for (int i : thrAdded)
|
||||
accum = __riscv_vwadd_wv_i16m8(
|
||||
accum, __riscv_vle8_v_i8m4(&threatWeights[i * Dimensions + tileOffset], vl), vl);
|
||||
__riscv_vse16_v_i16m8(&toAcc[tileOffset], accum, vl);
|
||||
|
||||
tileOffset += vl;
|
||||
}
|
||||
|
||||
tileOffset = 0;
|
||||
|
||||
while (tileOffset < PSQTBuckets)
|
||||
{
|
||||
usize vl = __riscv_vsetvl_e32m1(PSQTBuckets - tileOffset);
|
||||
|
||||
vint32m1_t accum = __riscv_vle32_v_i32m1(&fromPsqtAcc[tileOffset], vl);
|
||||
for (int i : psqRemoved)
|
||||
accum = __riscv_vsub_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&psqtWeights[i * PSQTBuckets + tileOffset], vl), vl);
|
||||
for (int i : psqAdded)
|
||||
accum = __riscv_vadd_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&psqtWeights[i * PSQTBuckets + tileOffset], vl), vl);
|
||||
for (int i : thrRemoved)
|
||||
accum = __riscv_vsub_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&threatPsqtWeights[i * PSQTBuckets + tileOffset], vl),
|
||||
vl);
|
||||
for (int i : thrAdded)
|
||||
accum = __riscv_vadd_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&threatPsqtWeights[i * PSQTBuckets + tileOffset], vl),
|
||||
vl);
|
||||
|
||||
__riscv_vse32_v_i32m1(&toPsqtAcc[tileOffset], accum, vl);
|
||||
|
||||
tileOffset += vl;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
toAcc = fromAcc;
|
||||
@@ -448,6 +506,25 @@ Bitboard get_changed_pieces(const std::array<Piece, SQUARE_NB>& oldPieces,
|
||||
}
|
||||
|
||||
return ~sameBB;
|
||||
#elif defined(USE_RVV)
|
||||
|
||||
#define IMPL(mx, bx) \
|
||||
return __riscv_vmv_x_s_u64m1_u64(__riscv_vreinterpret_v_u8m1_u64m1( \
|
||||
__riscv_vreinterpret_v_b##bx##_u8m1(__riscv_vmsne_vv_i8m##mx##_b##bx( \
|
||||
__riscv_vle8_v_i8m##mx(reinterpret_cast<const i8*>(oldPieces.data()), 64), \
|
||||
__riscv_vle8_v_i8m##mx(reinterpret_cast<const i8*>(newPieces.data()), 64), 64))))
|
||||
|
||||
|
||||
usize vl = __riscv_vsetvlmax_e8m1();
|
||||
if (vl >= 64)
|
||||
IMPL(1, 8);
|
||||
else if (vl == 32)
|
||||
IMPL(2, 4);
|
||||
else
|
||||
IMPL(4, 2);
|
||||
|
||||
#undef IMPL
|
||||
|
||||
#else
|
||||
Bitboard changed = 0;
|
||||
|
||||
@@ -596,6 +673,64 @@ void update_accumulator_refresh_cache(Color perspective,
|
||||
vec_store_psqt(&accTilePsqt[k], psqt[k]);
|
||||
}
|
||||
|
||||
#elif defined(USE_RVV)
|
||||
|
||||
const auto* weights = &featureTransformer.weights[0];
|
||||
const auto* threatWeights = &featureTransformer.threatWeights[0];
|
||||
const auto* psqtWeights = &featureTransformer.psqtWeights[0];
|
||||
const auto* threatPsqtWeights = &featureTransformer.threatPsqtWeights[0];
|
||||
|
||||
usize tileOffset = 0;
|
||||
|
||||
while (tileOffset < Dimensions)
|
||||
{
|
||||
usize vl = __riscv_vsetvl_e16m8(Dimensions - tileOffset);
|
||||
|
||||
vint16m8_t accum = __riscv_vle16_v_i16m8(&entry.accumulation[tileOffset], vl);
|
||||
for (int i : removed)
|
||||
accum = __riscv_vsub_vv_i16m8(
|
||||
accum, __riscv_vle16_v_i16m8(&weights[i * Dimensions + tileOffset], vl), vl);
|
||||
for (int i : added)
|
||||
accum = __riscv_vadd_vv_i16m8(
|
||||
accum, __riscv_vle16_v_i16m8(&weights[i * Dimensions + tileOffset], vl), vl);
|
||||
|
||||
__riscv_vse16_v_i16m8(&entry.accumulation[tileOffset], accum, vl);
|
||||
|
||||
for (int i : active)
|
||||
accum = __riscv_vwadd_wv_i16m8(
|
||||
accum, __riscv_vle8_v_i8m4(&threatWeights[i * Dimensions + tileOffset], vl), vl);
|
||||
|
||||
__riscv_vse16_v_i16m8(&accumulator.accumulation[perspective][tileOffset], accum, vl);
|
||||
|
||||
tileOffset += vl;
|
||||
}
|
||||
|
||||
tileOffset = 0;
|
||||
|
||||
while (tileOffset < PSQTBuckets)
|
||||
{
|
||||
usize vl = __riscv_vsetvl_e32m1(PSQTBuckets - tileOffset);
|
||||
|
||||
vint32m1_t accum = __riscv_vle32_v_i32m1(&entry.psqtAccumulation[tileOffset], vl);
|
||||
for (int i : removed)
|
||||
accum = __riscv_vsub_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&psqtWeights[i * PSQTBuckets + tileOffset], vl), vl);
|
||||
for (int i : added)
|
||||
accum = __riscv_vadd_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&psqtWeights[i * PSQTBuckets + tileOffset], vl), vl);
|
||||
|
||||
__riscv_vse32_v_i32m1(&entry.psqtAccumulation[tileOffset], accum, vl);
|
||||
|
||||
for (int i : active)
|
||||
accum = __riscv_vadd_vv_i32m1(
|
||||
accum, __riscv_vle32_v_i32m1(&threatPsqtWeights[i * PSQTBuckets + tileOffset], vl),
|
||||
vl);
|
||||
|
||||
__riscv_vse32_v_i32m1(&accumulator.psqtAccumulation[perspective][tileOffset], accum, vl);
|
||||
|
||||
tileOffset += vl;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
for (const auto index : removed)
|
||||
|
||||
@@ -342,6 +342,40 @@ class FeatureTransformer {
|
||||
cursor.record2(packed[0], packed[1]);
|
||||
}
|
||||
|
||||
#elif defined(USE_RVV)
|
||||
|
||||
usize j = 0;
|
||||
|
||||
while (j < HalfDimensions / 2)
|
||||
{
|
||||
usize vl = __riscv_vsetvl_e16m8(HalfDimensions / 2 - j);
|
||||
|
||||
vint16m8_t acc0 = __riscv_vle16_v_i16m8(&accumulation[perspectives[p]][j], vl);
|
||||
vint16m8_t acc1 =
|
||||
__riscv_vle16_v_i16m8(&accumulation[perspectives[p]][j + HalfDimensions / 2], vl);
|
||||
|
||||
acc0 = __riscv_vmax_vx_i16m8(acc0, 0, vl);
|
||||
acc1 = __riscv_vmax_vx_i16m8(acc1, 0, vl);
|
||||
|
||||
vuint8m4_t pa = __riscv_vnclipu_wx_u8m4(__riscv_vreinterpret_v_i16m8_u16m8(acc0), 0,
|
||||
__RISCV_VXRM_RDN, vl);
|
||||
vuint8m4_t pb = __riscv_vnclipu_wx_u8m4(__riscv_vreinterpret_v_i16m8_u16m8(acc1), 0,
|
||||
__RISCV_VXRM_RDN, vl);
|
||||
|
||||
vuint8m4_t hi = __riscv_vmulhu_vv_u8m4(pa, pb, vl);
|
||||
vuint8m4_t result = __riscv_vsrl_vx_u8m4(hi, 1, vl);
|
||||
|
||||
__riscv_vse8_v_u8m4(&output[offset + j], result, vl);
|
||||
j += vl;
|
||||
|
||||
// Record NNZ
|
||||
usize vl32 = vl / 4;
|
||||
vbool8_t nnzMask =
|
||||
__riscv_vmsne_vx_u32m4_b8(__riscv_vreinterpret_v_u8m4_u32m4(result), 0, vl32);
|
||||
__riscv_vsm_v_b8(cursor.out, nnzMask, vl32);
|
||||
cursor.out += vl32 / 8;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
for (IndexType j = 0; j < HalfDimensions / 2; ++j)
|
||||
|
||||
@@ -105,7 +105,7 @@ struct NNZInfo {
|
||||
NNZCursor make_cursor(bool perspective) { return {*this, perspective, count}; }
|
||||
#else
|
||||
// Each 8-bit chunk
|
||||
u8 bitset[(Dimensions + 31) / 32];
|
||||
alignas(8) u8 bitset[(Dimensions + 31) / 32];
|
||||
|
||||
struct NNZCursor {
|
||||
u8* out;
|
||||
|
||||
@@ -40,6 +40,10 @@
|
||||
|
||||
#elif defined(USE_LSX)
|
||||
#include <lsxintrin.h>
|
||||
|
||||
#elif defined(USE_RVV)
|
||||
#include <riscv_vector.h>
|
||||
|
||||
#endif
|
||||
|
||||
#include "../types.h"
|
||||
@@ -635,6 +639,35 @@ class SIMDTiling {
|
||||
static_assert(PSQTBuckets % PsqtTileHeight == 0, "PsqtTileHeight must divide PSQTBuckets");
|
||||
#endif
|
||||
};
|
||||
|
||||
#if defined(USE_RVV)
|
||||
|
||||
#define RVV_DEFINE_DPBUSD(A, W, H) \
|
||||
inline vint32##A##_t rvv_dpbusd_##A(vuint8##A##_t a, vint8##A##_t b, usize n) { \
|
||||
vint16##W##_t prod = __riscv_vwmulsu_vv_i16##W(b, a, 4 * n); \
|
||||
vuint32##W##_t prod32 = __riscv_vreinterpret_v_u16##W##_u32##W( \
|
||||
__riscv_vreinterpret_v_i16##W##_u16##W(prod)); \
|
||||
vint16##A##_t even = \
|
||||
__riscv_vreinterpret_v_u16##A##_i16##A(__riscv_vnsrl_wx_u16##A(prod32, 0, 2 * n)); \
|
||||
vint16##A##_t odd = \
|
||||
__riscv_vreinterpret_v_u16##A##_i16##A(__riscv_vnsrl_wx_u16##A(prod32, 16, 2 * n)); \
|
||||
vuint32##A##_t pairs = __riscv_vreinterpret_v_u16##A##_u32##A( \
|
||||
__riscv_vreinterpret_v_i16##A##_u16##A(__riscv_vadd_vv_i16##A(even, odd, 2 * n))); \
|
||||
vint16##H##_t lo = \
|
||||
__riscv_vreinterpret_v_u16##H##_i16##H(__riscv_vnsrl_wx_u16##H(pairs, 0, n)); \
|
||||
vint16##H##_t hi = \
|
||||
__riscv_vreinterpret_v_u16##H##_i16##H(__riscv_vnsrl_wx_u16##H(pairs, 16, n)); \
|
||||
return __riscv_vwadd_vv_i32##A(lo, hi, n); \
|
||||
}
|
||||
|
||||
RVV_DEFINE_DPBUSD(m1, m2, mf2)
|
||||
RVV_DEFINE_DPBUSD(m2, m4, m1)
|
||||
RVV_DEFINE_DPBUSD(m4, m8, m2)
|
||||
|
||||
#undef RVV_DEFINE_DPBUSD
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
Stockfish, a UCI chess playing engine derived from Glaurung 2.1
|
||||
Copyright (C) 2004-2026 The Stockfish developers (see AUTHORS file)
|
||||
Stockfish is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
Stockfish is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __linux__
|
||||
#include <sys/auxv.h>
|
||||
#include <sys/syscall.h>
|
||||
#include <unistd.h>
|
||||
#else
|
||||
#error This file is only supported on Linux
|
||||
#endif
|
||||
|
||||
#define DEFINE_BUILD(x) \
|
||||
namespace Stockfish_##x { \
|
||||
extern int main(int argc, char* argv[]); \
|
||||
} \
|
||||
extern "C" void (*__start_##x##_init[])(void); \
|
||||
extern "C" void (*__stop_##x##_init[])(void); \
|
||||
int entry_##x(int argc, char* argv[]) { \
|
||||
unsigned count = __stop_##x##_init - __start_##x##_init; \
|
||||
for (unsigned i = 0; i < count; i++) \
|
||||
__start_##x##_init[i](); \
|
||||
return Stockfish_##x::main(argc, argv); \
|
||||
}
|
||||
|
||||
DEFINE_BUILD(riscv64)
|
||||
DEFINE_BUILD(riscv64_rva23)
|
||||
|
||||
struct CpuFeatures {
|
||||
bool gcv; // GCV
|
||||
bool zbitmanip; // Zba + Zbb + Zbs
|
||||
bool zicond; // Zicond
|
||||
int vlen; // vector length in bits (valid only if gcv is true), always a power of two
|
||||
};
|
||||
|
||||
static CpuFeatures query_cpu_features() {
|
||||
unsigned long hwcap = getauxval(AT_HWCAP);
|
||||
constexpr long MASK_GCV = 0x20112d;
|
||||
|
||||
bool gcv = (hwcap & MASK_GCV) == MASK_GCV;
|
||||
int vlen = 0;
|
||||
if (gcv)
|
||||
{
|
||||
unsigned long vlenb;
|
||||
asm volatile("csrr %0, 0xc22" : "=r"(vlenb)); // 0xc22 = vlenb
|
||||
vlen = int(vlenb * 8);
|
||||
}
|
||||
|
||||
constexpr long NR_riscv_hwprobe = 258;
|
||||
constexpr int64_t KEY_IMA_EXT_0 = 4;
|
||||
constexpr uint64_t EXT_ZB = 1 << 3 | 1 << 4 | 1 << 5;
|
||||
constexpr uint64_t EXT_ZICOND = uint64_t(1) << 35;
|
||||
|
||||
struct {
|
||||
int64_t key;
|
||||
uint64_t value;
|
||||
} pair = {KEY_IMA_EXT_0, 0};
|
||||
|
||||
long rc = syscall(NR_riscv_hwprobe, &pair, 1UL, 0UL, nullptr, 0U);
|
||||
bool zbitmanip = false, zicond = false;
|
||||
|
||||
if (rc == 0 && pair.key == KEY_IMA_EXT_0)
|
||||
{
|
||||
zbitmanip = (pair.value & EXT_ZB) == EXT_ZB;
|
||||
zicond = (pair.value & EXT_ZICOND) == EXT_ZICOND;
|
||||
}
|
||||
|
||||
return CpuFeatures{.gcv = gcv, .zbitmanip = zbitmanip, .zicond = zicond, .vlen = vlen};
|
||||
}
|
||||
|
||||
|
||||
// Selects the most capable ISA variant supported by this CPU
|
||||
static int dispatch(const CpuFeatures& f, int argc, char* argv[]) {
|
||||
if (!f.gcv || !f.zbitmanip || !f.zicond || f.vlen < 128)
|
||||
return entry_riscv64(argc, argv);
|
||||
|
||||
return entry_riscv64_rva23(argc, argv);
|
||||
}
|
||||
|
||||
int main(int argc, char* argv[]) {
|
||||
CpuFeatures f = query_cpu_features();
|
||||
return dispatch(f, argc, argv);
|
||||
}
|
||||
Reference in New Issue
Block a user