[RfC] RISC-V port and universal binary

Performance on Spacemit K3, thanks @edolnx for testing

master:
Total time (ms) : 65200
Nodes searched  : 3493826
Nodes/second    : 53586

riscv-scalable-port:
Total time (ms) : 15834
Nodes searched  : 3493826
Nodes/second    : 220653

Also thanks to @camel-cdr for guidance on RVV programming, and https://cloud-v.co for supplying an RVV instance to test with

passed STC:
LLR: 2.81 (-2.94,2.94) <0.00,2.00>
Total: 1152 W: 527 L: 108 D: 517
Ptnml(0-2): 0, 17, 167, 348, 44
https://tests.stockfishchess.org/tests/view/6a39895b3036e45021aeb368

## Summary

We've had a `riscv64` target for a while, but haven't really optimized for it, in particular the vector extension (RVV).

RVV, like SVE, is based on a scalable vector system where the vector length ranges from 128 to 65536. In practice implementations are between 128 and 2048, and 256 bits is quite common (e.g. the Spacemit K3 system above). Unfortunately this doesn't fit well into the rest of our code which assumes a fixed vector length, so what I've done is bypass the `VECTOR` ifdef (which now basically means "FIXED_LENGTH_VECTOR") and just have RVV-specific paths.

The ability to explicitly control `vl` makes the code quite readable, in my opinion. We use LMUL>1 in most places to take advantage of multi-vector instructions. Generally the LMULs were chosen to best support a 256-bit vlen, which is very common, but by virtue of how the vlen control works, the code works with any vlen. In a couple places, i.e., `get_changed_pieces` and `AffineTransformSparseInput::propagate`, we have separate implementations depending on the vlen, because the optimal LMUL varies a lot between implementations.

One little wrinkle is that `load_as` is compiled to a sequence of byte loads, because although unaligned loads are legal in RVA23, the spec says that they *may* be extremely slow (even though they usually aren't, in actual hw), so compilers are conservative. Thus I aligned the relevant buffers and made the semantics of `load_as` that the operand is aligned, by adding a runtime assertion.

### Universal binary

Adding a universal binary is pretty easy and we can just cross-compile. There are two targets: baseline rv64gc and riscv64-rva23, which is actually a smaller subset of RVA23 that also works on some older processors that don't support the full thing. We use clang because GCC, until recently, has a nasty bug with LTO and RVV.

Like the universal ARM and x86 builds, we check all the builds in CI. In this case we run bench with multiple vlens, 128 through 1024.

In the meantime I deleted the existing broken and unused riscv64 tests.

### Follow-ups

- Optimizations
- zvdot4a8i path

closes https://github.com/official-stockfish/Stockfish/pull/6920

No functional change

src/universal/entry_riscv64.cpp

@@ -0,0 +1,96 @@
+/*
+  Stockfish, a UCI chess playing engine derived from Glaurung 2.1
+  Copyright (C) 2004-2026 The Stockfish developers (see AUTHORS file)
+  Stockfish is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+  Stockfish is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <stdint.h>
+
+#ifdef __linux__
+    #include <sys/auxv.h>
+    #include <sys/syscall.h>
+    #include <unistd.h>
+#else
+    #error This file is only supported on Linux
+#endif
+
+#define DEFINE_BUILD(x) \
+    namespace Stockfish_##x { \
+        extern int main(int argc, char* argv[]); \
+    } \
+    extern "C" void (*__start_##x##_init[])(void); \
+    extern "C" void (*__stop_##x##_init[])(void); \
+    int entry_##x(int argc, char* argv[]) { \
+        unsigned count = __stop_##x##_init - __start_##x##_init; \
+        for (unsigned i = 0; i < count; i++) \
+            __start_##x##_init[i](); \
+        return Stockfish_##x::main(argc, argv); \
+    }
+
+DEFINE_BUILD(riscv64)
+DEFINE_BUILD(riscv64_rva23)
+
+struct CpuFeatures {
+    bool gcv;        // GCV
+    bool zbitmanip;  // Zba + Zbb + Zbs
+    bool zicond;     // Zicond
+    int  vlen;       // vector length in bits (valid only if gcv is true), always a power of two
+};
+
+static CpuFeatures query_cpu_features() {
+    unsigned long  hwcap    = getauxval(AT_HWCAP);
+    constexpr long MASK_GCV = 0x20112d;
+
+    bool gcv  = (hwcap & MASK_GCV) == MASK_GCV;
+    int  vlen = 0;
+    if (gcv)
+    {
+        unsigned long vlenb;
+        asm volatile("csrr %0, 0xc22" : "=r"(vlenb));  // 0xc22 = vlenb
+        vlen = int(vlenb * 8);
+    }
+
+    constexpr long     NR_riscv_hwprobe = 258;
+    constexpr int64_t  KEY_IMA_EXT_0    = 4;
+    constexpr uint64_t EXT_ZB           = 1 << 3 | 1 << 4 | 1 << 5;
+    constexpr uint64_t EXT_ZICOND       = uint64_t(1) << 35;
+
+    struct {
+        int64_t  key;
+        uint64_t value;
+    } pair = {KEY_IMA_EXT_0, 0};
+
+    long rc        = syscall(NR_riscv_hwprobe, &pair, 1UL, 0UL, nullptr, 0U);
+    bool zbitmanip = false, zicond = false;
+
+    if (rc == 0 && pair.key == KEY_IMA_EXT_0)
+    {
+        zbitmanip = (pair.value & EXT_ZB) == EXT_ZB;
+        zicond    = (pair.value & EXT_ZICOND) == EXT_ZICOND;
+    }
+
+    return CpuFeatures{.gcv = gcv, .zbitmanip = zbitmanip, .zicond = zicond, .vlen = vlen};
+}
+
+
+// Selects the most capable ISA variant supported by this CPU
+static int dispatch(const CpuFeatures& f, int argc, char* argv[]) {
+    if (!f.gcv || !f.zbitmanip || !f.zicond || f.vlen < 128)
+        return entry_riscv64(argc, argv);
+
+    return entry_riscv64_rva23(argc, argv);
+}
+
+int main(int argc, char* argv[]) {
+    CpuFeatures f = query_cpu_features();
+    return dispatch(f, argc, argv);
+}