mirror of
https://github.com/official-stockfish/Stockfish.git
synced 2026-07-22 12:47:08 +00:00
anematodeandJoost VandeVondele
0d26c61ff2
also add -flax-vector-conversions=none to the build closes https://github.com/official-stockfish/Stockfish/pull/6587 No functional change
435 lines
15 KiB
C++
435 lines
15 KiB
C++
/*
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Stockfish, a UCI chess playing engine derived from Glaurung 2.1
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Copyright (C) 2004-2026 The Stockfish developers (see AUTHORS file)
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Stockfish is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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Stockfish is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NNUE_SIMD_H_INCLUDED
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#define NNUE_SIMD_H_INCLUDED
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#if defined(USE_AVX2)
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#include <immintrin.h>
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#elif defined(USE_SSE41)
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#include <smmintrin.h>
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#elif defined(USE_SSSE3)
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#include <tmmintrin.h>
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#elif defined(USE_SSE2)
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#include <emmintrin.h>
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#elif defined(USE_NEON)
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#include <arm_neon.h>
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#endif
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#include "../types.h"
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#include "nnue_common.h"
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namespace Stockfish::Eval::NNUE::SIMD {
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// If vector instructions are enabled, we update and refresh the
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// accumulator tile by tile such that each tile fits in the CPU's
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// vector registers.
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#define VECTOR
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#ifdef USE_AVX512
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using vec_t = __m512i;
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using vec_i8_t = __m256i;
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using vec128_t = __m128i;
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using psqt_vec_t = __m256i;
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using vec_uint_t = __m512i;
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#define vec_load(a) _mm512_load_si512(a)
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#define vec_store(a, b) _mm512_store_si512(a, b)
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#define vec_convert_8_16(a) _mm512_cvtepi8_epi16(a)
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#define vec_add_16(a, b) _mm512_add_epi16(a, b)
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#define vec_sub_16(a, b) _mm512_sub_epi16(a, b)
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#define vec_mulhi_16(a, b) _mm512_mulhi_epi16(a, b)
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#define vec_zero() _mm512_setzero_epi32()
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#define vec_set_16(a) _mm512_set1_epi16(a)
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#define vec_max_16(a, b) _mm512_max_epi16(a, b)
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#define vec_min_16(a, b) _mm512_min_epi16(a, b)
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#define vec_slli_16(a, b) _mm512_slli_epi16(a, b)
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// Inverse permuted at load time
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#define vec_packus_16(a, b) _mm512_packus_epi16(a, b)
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#define vec_load_psqt(a) _mm256_load_si256(a)
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#define vec_store_psqt(a, b) _mm256_store_si256(a, b)
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#define vec_add_psqt_32(a, b) _mm256_add_epi32(a, b)
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#define vec_sub_psqt_32(a, b) _mm256_sub_epi32(a, b)
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#define vec_zero_psqt() _mm256_setzero_si256()
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#ifdef USE_SSSE3
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#define vec_nnz(a) _mm512_cmpgt_epi32_mask(a, _mm512_setzero_si512())
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#endif
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#define vec128_zero _mm_setzero_si128()
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#define vec128_set_16(a) _mm_set1_epi16(a)
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#define vec128_load(a) _mm_load_si128(a)
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#define vec128_storeu(a, b) _mm_storeu_si128(a, b)
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#define vec128_add(a, b) _mm_add_epi16(a, b)
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#define NumRegistersSIMD 16
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#define MaxChunkSize 64
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#elif USE_AVX2
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using vec_t = __m256i;
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using vec_i8_t = __m128i;
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using vec128_t = __m128i;
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using psqt_vec_t = __m256i;
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using vec_uint_t = __m256i;
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#define vec_load(a) _mm256_load_si256(a)
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#define vec_store(a, b) _mm256_store_si256(a, b)
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#define vec_convert_8_16(a) _mm256_cvtepi8_epi16(a)
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#define vec_add_16(a, b) _mm256_add_epi16(a, b)
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#define vec_sub_16(a, b) _mm256_sub_epi16(a, b)
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#define vec_mulhi_16(a, b) _mm256_mulhi_epi16(a, b)
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#define vec_zero() _mm256_setzero_si256()
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#define vec_set_16(a) _mm256_set1_epi16(a)
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#define vec_max_16(a, b) _mm256_max_epi16(a, b)
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#define vec_min_16(a, b) _mm256_min_epi16(a, b)
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#define vec_slli_16(a, b) _mm256_slli_epi16(a, b)
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// Inverse permuted at load time
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#define vec_packus_16(a, b) _mm256_packus_epi16(a, b)
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#define vec_load_psqt(a) _mm256_load_si256(a)
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#define vec_store_psqt(a, b) _mm256_store_si256(a, b)
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#define vec_add_psqt_32(a, b) _mm256_add_epi32(a, b)
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#define vec_sub_psqt_32(a, b) _mm256_sub_epi32(a, b)
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#define vec_zero_psqt() _mm256_setzero_si256()
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#ifdef USE_SSSE3
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#if defined(USE_VNNI) && !defined(USE_AVXVNNI)
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#define vec_nnz(a) _mm256_cmpgt_epi32_mask(a, _mm256_setzero_si256())
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#else
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#define vec_nnz(a) \
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_mm256_movemask_ps( \
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_mm256_castsi256_ps(_mm256_cmpgt_epi32(a, _mm256_setzero_si256())))
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#endif
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#endif
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#define vec128_zero _mm_setzero_si128()
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#define vec128_set_16(a) _mm_set1_epi16(a)
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#define vec128_load(a) _mm_load_si128(a)
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#define vec128_storeu(a, b) _mm_storeu_si128(a, b)
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#define vec128_add(a, b) _mm_add_epi16(a, b)
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#define NumRegistersSIMD 12
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#define MaxChunkSize 32
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#elif USE_SSE2
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using vec_t = __m128i;
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using vec_i8_t = std::uint64_t; // for the correct size -- will be loaded into an xmm reg
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using vec128_t = __m128i;
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using psqt_vec_t = __m128i;
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using vec_uint_t = __m128i;
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#define vec_load(a) (*(a))
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#define vec_store(a, b) *(a) = (b)
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#define vec_add_16(a, b) _mm_add_epi16(a, b)
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#define vec_sub_16(a, b) _mm_sub_epi16(a, b)
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#define vec_mulhi_16(a, b) _mm_mulhi_epi16(a, b)
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#define vec_zero() _mm_setzero_si128()
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#define vec_set_16(a) _mm_set1_epi16(a)
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#define vec_max_16(a, b) _mm_max_epi16(a, b)
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#define vec_min_16(a, b) _mm_min_epi16(a, b)
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#define vec_slli_16(a, b) _mm_slli_epi16(a, b)
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#define vec_packus_16(a, b) _mm_packus_epi16(a, b)
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#define vec_load_psqt(a) (*(a))
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#define vec_store_psqt(a, b) *(a) = (b)
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#define vec_add_psqt_32(a, b) _mm_add_epi32(a, b)
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#define vec_sub_psqt_32(a, b) _mm_sub_epi32(a, b)
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#define vec_zero_psqt() _mm_setzero_si128()
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#ifdef USE_SSSE3
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#define vec_nnz(a) \
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_mm_movemask_ps(_mm_castsi128_ps(_mm_cmpgt_epi32(a, _mm_setzero_si128())))
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#endif
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#ifdef __i386__
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inline __m128i _mm_cvtsi64_si128(int64_t val) {
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return _mm_loadl_epi64(reinterpret_cast<const __m128i*>(&val));
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}
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#endif
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#ifdef USE_SSE41
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#define vec_convert_8_16(a) _mm_cvtepi8_epi16(_mm_cvtsi64_si128(static_cast<int64_t>(a)))
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#else
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// Credit: Yoshie2000
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inline __m128i vec_convert_8_16(uint64_t x) {
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__m128i v8 = _mm_cvtsi64_si128(static_cast<int64_t>(x));
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__m128i sign = _mm_cmpgt_epi8(_mm_setzero_si128(), v8);
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return _mm_unpacklo_epi8(v8, sign);
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}
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#endif
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#define vec128_zero _mm_setzero_si128()
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#define vec128_set_16(a) _mm_set1_epi16(a)
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#define vec128_load(a) _mm_load_si128(a)
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#define vec128_storeu(a, b) _mm_storeu_si128(a, b)
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#define vec128_add(a, b) _mm_add_epi16(a, b)
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#define NumRegistersSIMD (Is64Bit ? 12 : 6)
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#define MaxChunkSize 16
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#elif USE_NEON
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using vec_t = int16x8_t;
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using vec_i8_t = int8x16_t;
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using psqt_vec_t = int32x4_t;
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using vec128_t = uint16x8_t;
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using vec_uint_t = uint32x4_t;
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#define vec_load(a) (*(a))
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#define vec_store(a, b) *(a) = (b)
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#define vec_add_16(a, b) vaddq_s16(a, b)
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#define vec_sub_16(a, b) vsubq_s16(a, b)
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#define vec_mulhi_16(a, b) vqdmulhq_s16(a, b)
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#define vec_zero() vec_t{0}
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#define vec_set_16(a) vdupq_n_s16(a)
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#define vec_max_16(a, b) vmaxq_s16(a, b)
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#define vec_min_16(a, b) vminq_s16(a, b)
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#define vec_slli_16(a, b) vshlq_s16(a, vec_set_16(b))
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#define vec_packus_16(a, b) reinterpret_cast<vec_t>(vcombine_u8(vqmovun_s16(a), vqmovun_s16(b)))
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#define vec_load_psqt(a) (*(a))
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#define vec_store_psqt(a, b) *(a) = (b)
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#define vec_add_psqt_32(a, b) vaddq_s32(a, b)
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#define vec_sub_psqt_32(a, b) vsubq_s32(a, b)
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#define vec_zero_psqt() psqt_vec_t{0}
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static constexpr std::uint32_t Mask[4] = {1, 2, 4, 8};
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#define vec_nnz(a) vaddvq_u32(vandq_u32(vtstq_u32(a, a), vld1q_u32(Mask)))
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#define vec128_zero vdupq_n_u16(0)
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#define vec128_set_16(a) vdupq_n_u16(a)
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#define vec128_load(a) vld1q_u16(reinterpret_cast<const std::uint16_t*>(a))
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#define vec128_storeu(a, b) vst1q_u16(reinterpret_cast<std::uint16_t*>(a), b)
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#define vec128_add(a, b) vaddq_u16(a, b)
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#define NumRegistersSIMD 16
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#define MaxChunkSize 16
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#ifndef __aarch64__
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// Single instruction doesn't exist on 32-bit ARM
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inline int16x8_t vmovl_high_s8(int8x16_t val) { return vmovl_s8(vget_high_s8(val)); }
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#endif
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#else
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#undef VECTOR
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#endif
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struct Vec16Wrapper {
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#ifdef VECTOR
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using type = vec_t;
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static type add(const type& lhs, const type& rhs) { return vec_add_16(lhs, rhs); }
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static type sub(const type& lhs, const type& rhs) { return vec_sub_16(lhs, rhs); }
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#else
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using type = BiasType;
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static type add(const type& lhs, const type& rhs) { return lhs + rhs; }
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static type sub(const type& lhs, const type& rhs) { return lhs - rhs; }
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#endif
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};
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struct Vec32Wrapper {
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#ifdef VECTOR
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using type = psqt_vec_t;
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static type add(const type& lhs, const type& rhs) { return vec_add_psqt_32(lhs, rhs); }
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static type sub(const type& lhs, const type& rhs) { return vec_sub_psqt_32(lhs, rhs); }
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#else
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using type = PSQTWeightType;
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static type add(const type& lhs, const type& rhs) { return lhs + rhs; }
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static type sub(const type& lhs, const type& rhs) { return lhs - rhs; }
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#endif
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};
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enum UpdateOperation {
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Add,
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Sub
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};
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template<typename VecWrapper,
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UpdateOperation... ops,
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std::enable_if_t<sizeof...(ops) == 0, bool> = true>
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typename VecWrapper::type fused(const typename VecWrapper::type& in) {
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return in;
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}
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template<typename VecWrapper,
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UpdateOperation update_op,
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UpdateOperation... ops,
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typename T,
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typename... Ts,
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std::enable_if_t<is_all_same_v<typename VecWrapper::type, T, Ts...>, bool> = true,
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std::enable_if_t<sizeof...(ops) == sizeof...(Ts), bool> = true>
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typename VecWrapper::type
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fused(const typename VecWrapper::type& in, const T& operand, const Ts&... operands) {
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switch (update_op)
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{
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case Add :
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return fused<VecWrapper, ops...>(VecWrapper::add(in, operand), operands...);
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case Sub :
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return fused<VecWrapper, ops...>(VecWrapper::sub(in, operand), operands...);
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default :
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static_assert(update_op == Add || update_op == Sub,
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"Only Add and Sub are currently supported.");
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return typename VecWrapper::type();
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}
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}
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#if defined(USE_AVX512)
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[[maybe_unused]] static int m512_hadd(__m512i sum, int bias) {
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return _mm512_reduce_add_epi32(sum) + bias;
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}
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[[maybe_unused]] static void m512_add_dpbusd_epi32(__m512i& acc, __m512i a, __m512i b) {
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#if defined(USE_VNNI)
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acc = _mm512_dpbusd_epi32(acc, a, b);
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#else
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__m512i product0 = _mm512_maddubs_epi16(a, b);
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product0 = _mm512_madd_epi16(product0, _mm512_set1_epi16(1));
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acc = _mm512_add_epi32(acc, product0);
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#endif
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}
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#endif
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#if defined(USE_AVX2)
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[[maybe_unused]] static int m256_hadd(__m256i sum, int bias) {
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__m128i sum128 = _mm_add_epi32(_mm256_castsi256_si128(sum), _mm256_extracti128_si256(sum, 1));
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sum128 = _mm_add_epi32(sum128, _mm_shuffle_epi32(sum128, _MM_PERM_BADC));
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sum128 = _mm_add_epi32(sum128, _mm_shuffle_epi32(sum128, _MM_PERM_CDAB));
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return _mm_cvtsi128_si32(sum128) + bias;
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}
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[[maybe_unused]] static void m256_add_dpbusd_epi32(__m256i& acc, __m256i a, __m256i b) {
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#if defined(USE_VNNI)
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acc = _mm256_dpbusd_epi32(acc, a, b);
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#else
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__m256i product0 = _mm256_maddubs_epi16(a, b);
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product0 = _mm256_madd_epi16(product0, _mm256_set1_epi16(1));
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acc = _mm256_add_epi32(acc, product0);
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#endif
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}
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#endif
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#if defined(USE_SSSE3)
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[[maybe_unused]] static int m128_hadd(__m128i sum, int bias) {
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sum = _mm_add_epi32(sum, _mm_shuffle_epi32(sum, 0x4E)); //_MM_PERM_BADC
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sum = _mm_add_epi32(sum, _mm_shuffle_epi32(sum, 0xB1)); //_MM_PERM_CDAB
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return _mm_cvtsi128_si32(sum) + bias;
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}
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[[maybe_unused]] static void m128_add_dpbusd_epi32(__m128i& acc, __m128i a, __m128i b) {
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__m128i product0 = _mm_maddubs_epi16(a, b);
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product0 = _mm_madd_epi16(product0, _mm_set1_epi16(1));
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acc = _mm_add_epi32(acc, product0);
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}
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#endif
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#if defined(USE_NEON_DOTPROD)
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[[maybe_unused]] static void
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dotprod_m128_add_dpbusd_epi32(int32x4_t& acc, int8x16_t a, int8x16_t b) {
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acc = vdotq_s32(acc, a, b);
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}
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#endif
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#if defined(USE_NEON)
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[[maybe_unused]] static int neon_m128_reduce_add_epi32(int32x4_t s) {
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#if USE_NEON >= 8
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return vaddvq_s32(s);
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#else
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return s[0] + s[1] + s[2] + s[3];
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#endif
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}
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[[maybe_unused]] static int neon_m128_hadd(int32x4_t sum, int bias) {
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return neon_m128_reduce_add_epi32(sum) + bias;
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}
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#endif
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#if USE_NEON >= 8
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[[maybe_unused]] static void neon_m128_add_dpbusd_epi32(int32x4_t& acc, int8x16_t a, int8x16_t b) {
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int16x8_t product0 = vmull_s8(vget_low_s8(a), vget_low_s8(b));
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int16x8_t product1 = vmull_high_s8(a, b);
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int16x8_t sum = vpaddq_s16(product0, product1);
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acc = vpadalq_s16(acc, sum);
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}
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#endif
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// Compute optimal SIMD register count for feature transformer accumulation.
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template<IndexType TransformedFeatureWidth, IndexType HalfDimensions, IndexType PSQTBuckets>
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class SIMDTiling {
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#ifdef VECTOR
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// We use __m* types as template arguments, which causes GCC to emit warnings
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// about losing some attribute information. This is irrelevant to us as we
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// only take their size, so the following pragma are harmless.
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#if defined(__GNUC__)
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#pragma GCC diagnostic push
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#pragma GCC diagnostic ignored "-Wignored-attributes"
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#endif
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template<typename SIMDRegisterType, typename LaneType, int NumLanes, int MaxRegisters>
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static constexpr int BestRegisterCount() {
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constexpr std::size_t RegisterSize = sizeof(SIMDRegisterType);
|
|
constexpr std::size_t LaneSize = sizeof(LaneType);
|
|
|
|
static_assert(RegisterSize >= LaneSize);
|
|
static_assert(MaxRegisters <= NumRegistersSIMD);
|
|
static_assert(MaxRegisters > 0);
|
|
static_assert(NumRegistersSIMD > 0);
|
|
static_assert(RegisterSize % LaneSize == 0);
|
|
static_assert((NumLanes * LaneSize) % RegisterSize == 0);
|
|
|
|
const int ideal = (NumLanes * LaneSize) / RegisterSize;
|
|
if (ideal <= MaxRegisters)
|
|
return ideal;
|
|
|
|
// Look for the largest divisor of the ideal register count that is smaller than MaxRegisters
|
|
for (int divisor = MaxRegisters; divisor > 1; --divisor)
|
|
if (ideal % divisor == 0)
|
|
return divisor;
|
|
|
|
return 1;
|
|
}
|
|
|
|
#if defined(__GNUC__)
|
|
#pragma GCC diagnostic pop
|
|
#endif
|
|
|
|
public:
|
|
static constexpr int NumRegs =
|
|
BestRegisterCount<vec_t, WeightType, TransformedFeatureWidth, NumRegistersSIMD>();
|
|
static constexpr int NumPsqtRegs =
|
|
BestRegisterCount<psqt_vec_t, PSQTWeightType, PSQTBuckets, NumRegistersSIMD>();
|
|
|
|
static constexpr IndexType TileHeight = NumRegs * sizeof(vec_t) / 2;
|
|
static constexpr IndexType PsqtTileHeight = NumPsqtRegs * sizeof(psqt_vec_t) / 4;
|
|
|
|
static_assert(HalfDimensions % TileHeight == 0, "TileHeight must divide HalfDimensions");
|
|
static_assert(PSQTBuckets % PsqtTileHeight == 0, "PsqtTileHeight must divide PSQTBuckets");
|
|
#endif
|
|
};
|
|
}
|
|
|
|
#endif
|